The present application is related to concurrently filed non-provisional applications:
(i) by A. W. Hietala entitled Fractional-N Modulation with Analog IQ Interface; 
(ii) by B. T. Hunt and S. R. Humphreys entitled Dual-Modulus Prescaler; 
(iii) by S. R. Humphreys and A. W. Hietala entitled Fractional-N Synthesizer with Improved Noise Performance; and
(iv) by B. T. Hunt and S. R. Humphreys entitled True Single-Phase Flip-Flop, which non-provisional applications are assigned to the assignee of the present invention, and are hereby incorporated in the present application as if set forth in their entirety herein.
The present invention relates to digital electronic circuitry. More particularly, the present invention relates to digital accumulators. Still more particularly, the present invention relates to digital accumulators for use in fractional-N (F-N) synthesizers.
Phase-locked loop (PLL) frequency synthesis is a well-known technique for generating a variety of signals of predetermined frequency in many applications, e.g., digital radiotelephone systems. Briefly, the output of a voltage-controlled oscillator (VCO) is coupled to a frequency divider for providing one input to a phase detector. Another input to the phase detector is a reference signal from a fixed frequency source having high stability over a range of operating conditions. Differences in phase determined by the phase detector (typically reflected as charge pulses) are then filtered and applied to the VCO to control changes to the frequency of the VCO of such magnitude and sign as to reduce the detected phase difference.
Fractional-N (F-N) synthesizers based on the above-described PLL frequency synthesis techniques have been in favor for some time because, inter alia, they provide for non-integer division of the VCO output, thereby providing greater flexibility in choosing the VCO output frequency, and allowing the use of higher frequency reference sources with the concomitant potential for wider bandwidth and faster loop locking times. Other background aspects of RF synthesizers (and, in particular, F-N synthesizers), and their implementation and use, are presented in B. Razavi, RF Microelectronics, Prentice-Hall PTR, 1998, especially pp. 269-297, and in incorporated related patent application (i-v) cited above.
FIG. 1 shows a prior art F-N synthesizer arrangement in which a reference signal, e.g., from stable frequency source is applied on input 135 as one input to a phase detector 130. The other input to phase detector 130 is a frequency divided output from programmable divider 120 on path 125. Divider 120, in turn, receives an input from the output of VCO 100, which output is the frequency-controlled output of the synthesizer of FIG. 1. The integer part of the division ratio is applied on line 175 and input reflecting the fractional part of the division ratio is applied on line 155. More specifically, fractional sequence generator 150 responds to an applied fractional divisor input on lead 170 to provide a time-variable sequence of integer values, which, when applied through adder 160 allow a variable divisor to be realized in divider 120. Typically, fractional sequence generator 150 is clocked by the output of divider 120, and a new instantaneous divisor value is provided for each cycle of that clock. The overall effect of the application of this time-varying integer divisor in divider 120 is to apply a divisor to divider 120 that has an average value equal to the sum of the integer and fractional inputs on 175 and 170, respectively.
In operation, the prior art synthesizer of FIG. 1 controls the frequency of VCO 100 in response to varying integer divisors by applying a time-variable frequency divided version of the output from VCO 100 to phase detector 130. In comparing phase information for the frequency divided input from divider 120 with the reference signal on input 135, phase detector 130 develops an error signal that is smoothed in low pass loop filter 140 and applied to VCO 100 in such manner as to reduce the phase error between the reference signal and the frequency divided signal from divider 120. In doing so, the output from VCO 100 tracks the desired frequency variations specified by fractional inputs on input 170.
Overall, if the desired fractional output of the divider is represented as a numerator, C, and a denominator, D, then the output sequence, SEQ, from sequence generator 150 in FIG. 1 is given by
avg(SEQ)=C/D,
where avg) represents an averaging operation. When SEQ is added to the integer value appearing on 175 in FIG. 1, the instantaneous value of the divisor is given by
N[i]=Nint+SEQ[i],
where SEQ[i] is the instantaneous value of the sequence and Nint is the integer portion of the divisor presented on 175. Thus, the average of total divisor value N is given by
avg(N)=Nint+avg(SEQ)=Nint+C/D.
The fractional-n PLL then locks the VCO 100 in FIG. 1 to the frequency
Fvco=Fref.(Nint+C/D),
which has a resolution or step size given by
Fstep=Fref/D.
FIG. 2 shows a prior art fractional sequence generator 200 based generally on aspects of a F-N synthesizer circuit arrangement shown in U.S. Pat. No. 4,609,881 issued Sep. 2, 1986 to J. N. Wells, which patent is hereby incorporated by reference as if set forth in its entirety herein. The sequence generator of FIG. 2 includes an accumulator structure 210 having a plurality of accumulatorsxe2x80x94each comprising an n-bit bank of D flip-flops (an n-bit register), 230-i, i=1, 2, and 3 and a corresponding n-bit adder 225-i, i=1, 2, and 3. Adder 225-1 receives a fractional divisor value f (the least significant bits of a divisor of the form N.ƒ, where N is an integer) on the C input path 215 during a current clock cycle of the output of divider 120. Clock signals corresponding to the output of divider 120 are provided as inputs on Fv input 220. The value f on input 215 is added to the previous contents of n-bit register 230-1 and the result is stored in register 230-1. In addition, when register 230-1 overflows (provides a carry-out indication on recombination output CO1), that signal is immediately applied to adder 240 at an input labeled +1. The set of recombination paths is conveniently referred to as recombination network 205.
As further shown in FIG. 2, the sum stored in register 230-1 is also provided as an input to adder 225-2, where it is combined with the prior contents of register 230-2 during the following clock cycle. Again, the result of the addition is stored back in register 230-2 and a carry indication is provided on recombination path CO2 when overflow of adder 230-2 occurs is applied to an input to adder 240 labeled +1. In addition, the same overflow signal on CO2 is applied to a xe2x88x921 input to adder 240 after a delay of one additional clock cycle. Such additional delay of one clock cycle is provided by delay flip-flop 250.
In similar fashion, adder 230-3 receives the result of the addition performed at adder 230-2 and adds it to the prior contents of register 230-3. Again, the result of the addition is stored back to register 230-3, and, when a carry-out occurs from adder 225-3, recombination path CO3 supplies the carry-out signal to a +1 input to adder 240. In addition, the CO3 recombination path provides the carry-out indication to delay flip-flop 260, thereby providing the carry out signal to a xe2x88x922 input to adder 240 after an additional clock cycle. Further, the delayed CO3 signal on the output of flip-flop 260 is also provided as an input to delay flip-flop 270 where it provides the carry-out signal to a +1 input to adder 240 after yet another clock cycle (a total delay of two clock cycles).
Each of the carry-out signals from adders 225-i causes adder 240 to provide an output on SEQ path 245 to temporarily increment or decrement the integer divisor applied through adder 160 to divider 120 in FIG. 1. The magnitude and sign of an increment or decrement during any clock cycle is determined as the sum of increments and decrements indicated by the weights for all recombination paths supplying carry-out signals during that clock cycle. The weights correspond to sequences associated with a Pascal""s Triangle. These integer divisor changes advantageously average to the desired fractional portion over time. See further the discussion of Pascal sequence coefficients in incorporated U.S. Pat. No. 4,609,881.
In the accumulator structure 210 of the fractional sequence generator of FIG. 2, the denominator, D, is equal to the range (max value-min value) of the digital adders 225-i. When the number of bits in D is n, then D=2n. Thus, the accumulator structure of FIG. 2 typically forces the denominator to assume a fixed value. If the number of bits in the adder can be selected, then different values, all equal to a power of 2 can be achieved. However, many applications of F-N synthesizers, e.g., those employing automatic frequency control (AFC) and/or digital modulation, desirably include greater flexibility in the selection of frequency resolution or frequency step size than is provided using prior art dividers. Otherwise, additional scaling operations become necessary in other parts of an overall system and, especially in AFC applications, gain of the control loop depends in part on frequency step size. It is therefore desired that a F-N synthesizer include a fractional sequence generator with an accumulator structure having a variable or programmable denominator, without also significantly increasing circuit complexity, delay, and power consumption.
Limitations of the prior are overcome and a technical advance is made in accordance with the present invention, typical embodiments of which are described below.
In accordance with one illustrative embodiment of the present invention a fractional sequence generator for use in a F-N synthesizer comprises a multi-accumulator structure providing a plurality of carry-out signals for application to an adder through a recombination network, thereby to generate an output fractional sequence, SEQ (hereinafter, S), having an average value given by avg(S)=C/D, where C/D is the desired fractional part of the divisor. Advantageously, the denominator, D, is programmable as a value not restricted to powers of 2 or other particular value.
In accordance with an aspect of illustrative embodiments of the present invention, contents of a n-bit accumulator in each of the accumulators is augmented by a function of the programmable denominator value upon a carry-out of the associated n-bit adder in that accumulator. Illustratively, for a given denominator, D, the offset applied upon carry-out of the accumulator is chosen as 2nxe2x88x92D. This offset is conveniently generated at the ith accumulator using a multiplexer supplying a value of 2nxe2x88x921 when the carry-out from the ith accumulator assumes a logical 1 value, and supplying a zero value otherwise. The output of the multiplexer, in turn, is conveniently summed in an adder with the current contents of the n-bit register storing the accumulator contents (after rollover). A result of augmenting accumulator values in accordance with the programmable function of D is that rollover timing can be selected to achieve any desired C/D.